PCI express slot. Existing connectors and types of ports. Types of devices using PCI Express x2, x4, x8, x12, x16 and x32

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    Unlike the PCI standard, which used a common bus for data transfer with multiple devices connected in parallel, PCI Express is, in general, a packet network with a star topology.

    PCI Express devices communicate with each other through a medium formed by switches, with each device directly connected by a point-to-point connection to the switch.

    In addition, the PCI Express bus supports:

    • guaranteed bandwidth (QoS);
    • energy management;
    • monitoring the integrity of transmitted data.

    The PCI Express bus is intended to be used only as a local bus. Since the PCI Express software model is largely inherited from PCI, existing systems and controllers can be modified to use the PCI bus Express replacement only physical level, without modification software. The high peak performance of the PCI Express bus allows it to be used instead of AGP buses, and even more so PCI and PCI-X. De facto, PCI Express replaced these buses in personal computers.

    Connectors

    • MiniCard (Mini PCIe) - replacement for the Mini PCI form factor. The Mini Card connector supports the following buses: x1 PCIe, USB 2.0 and SMBus.
    • ExpressCard - similar to PCMCIA form factor. The ExpressCard connector supports x1 PCIe and USB 2.0 buses; ExpressCard cards support hot plugging.
    • AdvancedTCA is a form factor for telecommunications equipment.
    • Mobile PCI Express Module (MXM) is an industrial form factor created for laptops by NVIDIA. It is used to connect graphics accelerators.
    • PCI Express cable specifications allow the length of a single connection to reach tens of meters, which makes it possible to create computers that peripherals which are located at a considerable distance.
    • StackPC - specification for building stackable computer systems. This specification describes the StackPC, FPE expansion connectors and their relative positions.

    PCI Express X1

    Mini PCI-E

    Mini PCI Express is a PCI Express bus format for portable devices.

    Many peripheral devices are available for this connector standard:

    SSD Mini PCI Express

    • Power supply 3.3V

    ExpressCard

    ExpressCard slots are currently (November 2010) used to connect:

    • SSD storage boards
    • Video cards
    • 1394/FireWire (iLINK) controllers
    • Docking stations
    • Measuring instruments
    • In memory
    • Memory card adapters (CF, MS, SD, xD, etc.)
    • Mice
    • Network adapters
    • Parallel ports
    • PC Card/PCMCIA adapters
    • PCI extensions
    • PCI Express expansions
    • Remote control
    • SATA controllers
    • Serial ports
    • SmartCard adapters
    • TV tuners
    • USB controllers
    • Wireless network adapters WiFi
    • Wireless broadband Internet adapters (3G, CDMA, EVDO, GPRS, UMTS, etc.)
    • Sound cards for home multimedia and professional audio interfaces.

    Protocol description

    To connect a PCI Express device, a bidirectional point-to-point serial connection is used, called a line (English lane - strip, row); this is in stark contrast to PCI, in which all devices are connected to a common 32-bit parallel bidirectional bus.

    Competing protocols

    In addition to PCI Express, there are a number of high-speed standardized serial interfaces, here are just a few: HyperTransport, InfiniBand, RapidIO, and StarFabric. Each interface has its supporters among industrial companies, since significant sums have already been spent on the development of protocol specifications, and each consortium seeks to emphasize the advantages of its particular interface over others.

    A standardized high-speed interface, on the one hand, must be flexible and extensible, and on the other hand, must provide low latency and low overhead (that is, the share of packet overhead should not be large). In essence, the differences between interfaces lie precisely in the compromise chosen by the developers of a particular interface between these two conflicting requirements.

    For example, additional service routing information in a packet allows you to organize complex and flexible packet routing, but it increases the overhead of processing the packet, the interface throughput also decreases, and the software that initializes and configures devices connected to the interface becomes more complicated. If it is necessary to ensure hot plugging of devices, special software is required that would monitor changes in the network topology. Examples of interfaces that accommodate this are RapidIO, InfiniBand and StarFabric.

    At the same time, by shortening packets, it is possible to reduce the delay in data transfer, which is an important requirement for a memory interface. But the small size of packets leads to the fact that the proportion of packet overhead fields increases, which reduces the effective throughput of the interface. An example of this type of interface is HyperTransport.

    The position of PCI Express is between the described approaches, since the PCI Express bus is designed to operate as a local bus, rather than a processor-memory bus or a complex routable network. In addition, PCI Express was originally conceived as a bus that was logically compatible with the PCI bus, which also introduced its own limitations.

    Introduction

    Moore's Law states that the number of transistors on a silicon chip that is profitable to produce doubles every couple of years. But don't think that processor speeds also double every couple of years. This is a common misconception among many, and users often expect PC performance to scale exponentially.

    However, as you probably noticed, the top processors on the market have been stuck at the level between 3 and 4 GHz for about six years now. And the computer industry had to look for new ways to increase computing performance. The most important of these methods is to maintain a balance between platform components that use the PCI Express bus, an open standard that allows high-speed video cards, expansion cards and other components to exchange information. And the PCI Express interface is no less important for scaling performance than multi-core processors. While dual-core, quad-core, and six-core processors can only be loaded with thread-optimized applications, every program installed on your computer interacts in some way with components connected via PCI Express.


    Many journalists and experts expected that motherboards and chipsets supporting the next generation PCI Express 3.0 interface would appear in the first quarter of 2010. Unfortunately, backward compatibility problems delayed the release of PCI Express 3.0, and today it has already been six months, but we are still waiting official information regarding the publication of the new standard.

    However, we talked to the PCI-SIG (Special Interest Group, which is responsible for the PCI and PCI Express standards), which allowed us to get some answers.

    PCI Express 3.0: plans

    Al Yanes, President and Chairman of PCI-SIG, and Ramin Neshati, Chairman of PCI-SIG Serial Communications Workgroup, shared current plans for the implementation of PCI Express 3.0.

    Click on the picture to enlarge.

    On June 23, 2010, version 0.71 of the PCI Express 3.0 specification was released. Jans argued that version 0.71 should fix all the backwards compatibility issues that led to the initial delay. Neshati noted that the main compatibility issue was the "DC wandering" feature, which he explained was that PCI Express 2.0 and earlier devices "didn't provide the necessary 0s and 1s" to comply with the PCI Express 3.0 interface.

    Today, with the backward compatibility issues resolved, PCI-SIG is ready to release the 0.9 baseline "later this summer." And after this basic version, version 1.0 is expected in the fourth quarter of this year.

    Of course, the most intriguing question is when PCI Express 3.0 motherboards will hit store shelves. Neshati noted that he expects the first products to appear in the first quarter of 2011 (triangle "FYI" in the picture with the plan).

    Neshati added that between versions 0.9 and 1.0 there should be no changes at the silicon level (that is, all changes will affect only software and firmware), so some products should reach the market before the final 1.0 specification. And products can already be certified to PCI-SIG's "Integrator's List" (triangle "IL"), which is a variant of the PCI-SIG compliance logo.

    Neshati jokingly referred to the third quarter of 2011 as the "Fry's and Buy" date (probably referring to Frys.com, Buy.com or Best Buy). That is, during this period we should expect the appearance of a large number of products with PCI Express 3.0 support in retail stores and online stores.

    PCI Express 3.0: Designed for Speed

    For end users, the main difference between PCI Express 2.0 and PCI Express 3.0 will be the significant increase in maximum throughput. PCI Express 2.0 has a signal transfer rate of 5 GT/s, which means the throughput is 500 MB/s for each line. Thus, the main PCI Express 2.0 graphics slot, which typically uses 16 lanes, provides bidirectional throughput of up to 8 GB/s.

    With PCI Express 3.0 we will get double these figures. PCI Express 3.0 uses a signal speed of 8 GT/s, which gives a throughput of 1 GB/s per lane. Thus, the main video card slot will receive a throughput of up to 16 GB/s.

    At first glance, increasing the signal speed from 5 GT/s to 8 GT/s does not seem like a doubling. However, the PCI Express 2.0 standard uses an 8b/10b encoding scheme, where 8 bits of data are transferred as 10-bit characters for the error correction algorithm. As a result, we get 20% redundancy, that is, a reduction in useful throughput.

    PCI Express 3.0 moves to a much more efficient 128b/130b encoding scheme, eliminating 20% ​​redundancy. Therefore, 8 GT/s is no longer a “theoretical” speed; This is an actual rate comparable in performance to the 10 GT/s signal rate if the 8b/10b encoding principle were used.

    Click on the picture to enlarge.

    We asked Jans about devices that will require an increase in speed. He replied that they would include "PLX switches, 40 Gbps Ethernet controllers, InfiniBand, solid state devices, which are becoming increasingly popular, and, of course, video cards." He added, "We haven't run out of innovations, they don't happen statically, they're a continuous stream," paving the way for further improvements in future versions of the PCI Express interface.

    Analysis: Where will we use PCI Express 3.0?

    Drives

    AMD has already integrated support for SATA 6 Gb/s into its 8th line of chipsets, and motherboard manufacturers are adding USB 3.0 controllers. Intel is a little behind in this area, since it does not support USB 3.0 or SATA 6 Gb/s in its chipsets (we already have preliminary samples of P67 motherboards in our laboratory, and they have support for SATA 6 Gb/s, but USB 3.0 in this generation we will not receive). However, as we have repeatedly seen in the confrontation between AMD and Intel, AMD's innovations often inspire Intel. Given the interface speeds of next-generation drives and peripherals, there is no need yet to migrate any of the technologies to PCI Express 3.0. For both USB 3.0 (5 Gbit/s) and SATA 6 Gbit/s (no drives have yet appeared that would fit the limits of this interface), one PCI Express line of the second generation will be sufficient.

    Of course, when it comes to drives, the interaction between drives and controllers is only part of the story. Imagine an array of several SSDs with a SATA 6 Gb/s interface on a chipset when RAID array 0 could potentially load the single Gen 2 PCI Express lane that most motherboard manufacturers use to connect the controller. So you can decide whether USB 3.0 and SATA 6 Gb/s interfaces can really require PCI Express 3.0 support after some simple calculations.

    Click on the picture to enlarge.

    As we already mentioned, the USB 3.0 interface gives a maximum speed of 5 Gbps. But like the PCI Express 2.1 standard, USB 3.0 uses 8b/10b encoding, which means the actual peak speed is 4 Gbps. Divide the bits by eight to convert to bytes, and you get a peak throughput of 500 MB/s - exactly the same as a single lane of the current PCI Express 2.1 standard. SATA 6 Gb/s operates at 6 Gb/s, but it also uses an 8b/10b encoding scheme, which turns the theoretical 6 Gb/s into an actual 4.8 Gb/s. Again, convert this value to bytes and you get 600 MB/s or 20% more than a PCI Express 2.0 lane can provide.

    However, the problem lies in the fact that even the fastest SSDs today cannot fully load a SATA 3 Gb/s connection. The peripherals do not even come close to the load of the USB 3.0 interface, the same can be said about the latest generation of SATA 6 Gb/s. At least today, the PCI Express 3.0 interface is not necessary for its active promotion in the platform market. But let's hope that as Intel moves to producing third-generation NAND flash memory, clock speeds will increase and we'll get devices capable of exceeding the 3 Gbps level of second-generation SATA ports.

    Video cards

    We conducted our own research on the impact of PCI Express bandwidth on video card performance - after PCI Express 2.0 entered the market , at the beginning of 2010, and also recently. As we have found, it is very difficult to load the x16 bandwidth, which is this moment available on PCI Express 2.1 motherboards. You'll need a multi-GPU setup or an extreme high-end graphics card on a single GPU to be able to tell the difference between x8 and x16 connections.

    We asked AMD and Nvidia to comment on the need for PCI Express 3.0 - will this speedy bus be required to unlock the full performance potential of next-generation graphics cards? An AMD spokesperson told us they couldn't comment at this time.


    Click on the picture to enlarge.

    An Nvidia spokesperson was more accommodating: "Nvidia played a key industry role in the development of PCI Express 3.0, which is expected to double the throughput of the current generation (2.0) standard. When significant increases in throughput like this occur, applications emerge that can "Consumers and professionals will benefit from the new standard with increased graphics and compute performance in GPU-equipped laptops, desktops, workstations and servers."

    Perhaps the key phrase is “there will be applications that can use them.” It looks like nothing is getting smaller in the graphics world. Displays are getting larger, high resolution is replacing standard definition, and textures in games are becoming more detailed and intriguing. Today we don't believe that even the latest high-end graphics cards have a need to use a PCI Express 3.0 interface with 16 lanes. But year after year, enthusiasts see history repeating itself as advances in technology pave the way for new ways to harness “thicker pipes.” We may see an explosion of applications that will make GPU computing more mainstream. Or, perhaps, the drop in performance that is observed when the video card memory goes beyond the limits, when swapping from system memory begins, will no longer be so noticeable in mass-market and low-end products. In any case, we will have to see the innovations that PCI Express 3.0 will allow AMD and Nvidia to implement.

    Motherboard Component Connections

    AMD and Intel are always very reluctant to share information about the interfaces they use to connect chipset components or logical “bricks” in the north/south bridges. We know the speed at which these interfaces operate and that they are designed to avoid bottlenecks as much as possible. Sometimes we know who made a certain part of the system logic, for example, AMD used a SATA controller based on Silicon Logic design in the SB600. But the technologies used to bridge the gaps between components often remain blind spots. PCI Express 3.0 certainly seems like a very attractive solution, similar to the A-Link interface that AMD uses.

    Recent appearance USB controllers 3.0 and SATA 6 Gb/s on a large number of motherboards also allows us to assess the situation. Since the Intel X58 chipset does not provide native support for either of the two technologies, companies such as Gigabyte have to integrate controllers onto motherboards using available lines to connect them.

    At the mother's Gigabyte boards EX58-UD5 does not support either USB 3.0 or SATA 6 Gb/s. However, it does have a x4 PCI Express slot.

    Click on the picture to enlarge.

    Gigabyte replaced motherboard EX58-UD5 new model X58A-UD5, which has support for two USB 3.0 ports and two SATA 6 Gb/s ports. Where did Gigabyte find the bandwidth to support these two technologies? The company took one PCI Express 2.0 line for each controller, reducing the ability to install expansion cards, but at the same time enriching the functionality of the motherboard.

    Other than the addition of USB 3.0 and SATA 6Gbps, the only noticeable difference between the two motherboards is the removal of the x4 slot.

    Click on the picture to enlarge.

    Will the PCI Express 3.0 interface, like the standards before it, allow future technologies and controllers to be added to motherboards that will not be present in the current generations of chipsets in an integrated form? It seems to us that it will be so.

    CUDA and parallel computing

    We are entering the era of desktop supercomputing. Our systems work GPUs with intensive parallel data processing, as well as power supplies and motherboards capable of supporting simultaneous operation of up to four video cards. Nvidia CUDA technology allows you to transform a video card into a tool for programmers to perform calculations not only in games, but also in scientific fields and engineering applications. The programming interface has already proven itself perfectly in development of various solutions for the corporate sector, including image processing in medicine, mathematics, oil and gas exploration work.

    Click on the picture to enlarge.

    We asked OpenGL programmer Terry Welsh from the company Really Slick Screensavers about PCI Express 3.0 and GPU computing. Terry told us that "PCI Express has taken a nice leap, and I like that developers are doubling the bandwidth whenever they want - like with version 3.0. However, in the projects I work on, I don't expect to see any difference. Most My work is related to flight simulators, but they tend to come down to memory and I/O performance hard drive; The graphics bus is not a bottleneck at all. But I can easily foresee that PCI Express 3.0 will drive significant advancements in the GPU computing space; for people who do scientific work with large amounts of data."

    Click on the picture to enlarge.

    The ability to double data transfer rates when running math-intensive workloads is certainly motivating the development of CUDA and Fusion. And this is one of the most promising areas for the upcoming PCI Express 3.0 interface.

    Any gamer with Intel chipset P55 can talk about the advantages and disadvantages of the Intel P55 compared to the Intel X58 chipset. Advantage: Most P55 chipset motherboards are more reasonably priced than Intel X58 models (in general, of course). Disadvantage: the P55 has minimal PCI Express connectivity; the main task is assigned to Intel Clarkdale and Lynnfield processors, which have 16 second-generation PCIe lanes in the CPU itself. Meanwhile, the X58 boasts 36 PCI Express 2.0 lanes.

    For P55 buyers who wish to use two graphics cards, they will have to be connected via x8 lanes each. If you want to add a third video card to the Intel P55 platform, you will have to use chipset lines - but, unfortunately, they are limited by the speed of the first generation, and the chipset can allocate a maximum of four lines for an expansion slot.

    When we asked PCI-SIG's Al Jans how many lanes we could expect in PCI Express 3.0-enabled chipsets from AMD and Intel, he said it was "proprietary information" that he "cannot disclose." Of course, we did not expect to receive an answer, but it was still worth asking the question. However, it is unlikely that AMD and Intel, which are part of the PCI-SIG Board of Directors, would invest time and money in PCI Express 3.0 if they planned to use new standard PCI Express is simply a means of reducing the number of lanes. It seems to us that in the future, AMD and Intel chipsets will continue to be segmented in the same way as we see today, high-end platforms will have enough capabilities to connect a pair of video cards with a full x16 interface, and the number of lines will be reduced for mass market chipsets.

    Imagine a chipset similar to the Intel P55, but with 16 PCI Express 3.0 lanes available. Since these 16 lanes are twice as fast as PCI Express 2.0, we get the equivalent of 32 lanes of the old standard. In such a situation, it will be up to Intel whether it wants to make the chipset compatible with 3-way and 4-way GPU configurations. Unfortunately, as we already know, the chipsets of the following Intel generation P67 and X68 will be limited to PCIe 2.0 support (and Sandy processors Bridge will be similarly limited to supporting 16 lanes on-chip).

    In addition to CUDA/Fusion parallel computing, we are also seeing an increase in the capabilities of mass market systems due to the increased communication speed of PCI Express 3.0 components - we think there is considerable potential here too. Without a doubt, PCI Express 3.0 will improve the capabilities of low-cost motherboards, which in the previous generation were only available to high-end platforms. And high-end platforms that have PCI Express 3.0 at their disposal will allow us to set new performance records thanks to innovations in graphics, storage and networking technologies that can use the available bus bandwidth.

    In the spring of 1991, Intel completed development of the first prototype version of the PCI bus. The engineers were tasked with developing an inexpensive and high-performance solution that would realize the capabilities of the 486, Pentium and Pentium Pro processors. In addition, it was necessary to take into account the mistakes made by VESA when designing the VLB bus (the electrical load did not allow connecting more than 3 expansion cards), and also to implement automatic setup devices.

    In 1992, the first version of the PCI bus appeared, Intel announced that the bus standard would be open, and created the PCI Special Interest Group. Thanks to this, any interested developer has the opportunity to create devices for the PCI bus without having to purchase a license. The first version of the bus had a clock frequency of 33 MHz, could be 32- or 64-bit, and devices could operate with signals of 5 V or 3.3 V. Theoretically, the bus throughput was 133 MB / s, but in reality the throughput was about 80 MB/s

    Main characteristics:


    • bus frequency - 33.33 or 66.66 MHz, synchronous transmission;
    • bus width - 32 or 64 bits, multiplexed bus (address and data are transmitted over the same lines);
    • peak throughput for the 32-bit version operating at 33.33 MHz is 133 MB/s;
    • memory address space - 32 bits (4 bytes);
    • address space of I/O ports - 32 bits (4 bytes);
    • configuration address space (for one function) - 256 bytes;
    • voltage - 3.3 or 5 V.

    Photos of connectors:

    MiniPCI - 124 pin
    MiniPCI Express MiniSata/mSATA - 52 pin
    Apple MBA SSD, 2012
    Apple SSD, 2012
    Apple PCIe SSD
    MXM, Graphics Card, 230 / 232 pin

    MXM2 NGIFF 75 pins

    KEY A PCIe x2

    KEY B PCIe x4 Sata SMBus
    MXM3, Graphics Card, 314 pin
    PCI 5V
    PCI Universal
    PCI-X 5v
    AGP Universal
    AGP 3.3 v
    AGP 3.3 v + ADS Power
    PCIe x1
    PCIe x16
    Custom PCIe
    ISA 8bit

    ISA 16bit
    eISA
    VESA
    NuBus
    PDS
    PDS
    Apple II/GS Expasion slot
    PC/XT/AT expasion bus 8 bit
    ISA (industry standard architecture) - 16 bit
    eISA
    MBA - Micro Bus architecture 16 bit
    MBA - Micro Bus architecture with 16 bit video
    MBA - Micro Bus architecture 32 bit
    MBA - Micro Bus architecture with 32 bit video
    ISA 16 + VLB (VESA)
    Processor Direct Slot PDS
    601 Processor Direct Slot PDS
    LC Processor Direct Slot PERCH
    NuBus
    PCI (Peripheral Computer Interconnect) - 5v
    PCI 3.3v
    CNR (Communications / network riser)
    AMR (Audio/Modem Riser)
    ACR (Advanced communication riser)
    PCI-X (Peripheral PCI) 3.3v
    PCI-X 5v
    PCI 5v + RAID option - ARO
    AGP 3.3v
    AGP 1.5v
    AGP Universal
    AGP Pro 1.5v
    AGP Pro 1.5v+ADC power
    PCIe (peripheral component interconnect express) x1
    PCIe x4
    PCIe x8
    PCIe x16

    PCI 2.0

    The first version of the basic standard to become widespread used both cards and slots with a signal voltage of only 5 volts. Peak throughput - 133 MB/s.

    PCI 2.1 - 3.0

    They differed from version 2.0 by the possibility of simultaneous operation of several bus masters (English bus-master, the so-called competitive mode), as well as the appearance of universal expansion cards capable of operating both in slots using a voltage of 5 volts, and in slots using 3 .3 volts (with a frequency of 33 and 66 MHz, respectively). Peak throughput for 33 MHz is 133 MB/s, and for 66 MHz it is 266 MB/s.

    • Version 2.1 - work with cards designed for a voltage of 3.3 volts, and the presence of appropriate power lines were optional.
    • Version 2.2 - expansion cards made in accordance with these standards have a universal power connector key and are able to work in many later types of PCI bus slots, as well as, in some cases, in version 2.1 slots.
    • Version 2.3 - Incompatible with PCI cards designed to use 5 volts, despite the continued use of 32-bit slots with a 5 volt key. Expansion cards have universal connector, but are not able to work in 5-volt slots of earlier versions (up to 2.1 inclusive).
    • Version 3.0 - completes the transition to 3.3 volt PCI cards, 5 volt PCI cards are no longer supported.

    PCI 64

    An extension of the basic PCI standard, introduced in version 2.1, that doubles the number of data lanes, and therefore the throughput. The PCI 64 slot is an extended version of the regular PCI slot. Formally, the compatibility of 32-bit cards with 64-bit slots (provided there is a common supported signal voltage) is full, but the compatibility of a 64-bit card with 32-bit slots is limited (in any case there will be a loss of performance). Works for clock frequency 33 MHz. Peak throughput - 266 MB/s.

    • Version 1 - uses a 64-bit PCI slot and a voltage of 5 volts.
    • Version 2 - uses a 64-bit PCI slot and a voltage of 3.3 volts.

    PCI 66

    PCI 66 is a 66 MHz evolution of PCI 64; uses 3.3 volts in the slot; the cards have a universal or 3.3 V form factor. Peak throughput is 533 MB/s.

    PCI 64/66

    The combination of PCI 64 and PCI 66 allows for four times the data transfer speed of the basic PCI standard; uses 64-bit 3.3V slots, compatible only with universal ones, and 3.3V 32-bit expansion cards. PCI64/66 standard cards have either a universal (but with limited compatibility with 32-bit slots) or a 3.3-volt form factor (the latter option is fundamentally incompatible with 32-bit 33-MHz slots of popular standards). Peak throughput - 533 MB/s.

    PCI-X

    PCI-X 1.0 is an expansion of the PCI64 bus with the addition of two new operating frequencies, 100 and 133 MHz, as well as a separate transaction mechanism to improve performance when multiple devices operate simultaneously. Generally backward compatible with all 3.3V and generic PCI cards. PCI-X cards are usually implemented in a 64-bit 3.3B format and have limited backward compatibility with PCI64/66 slots, and some PCI-X cards are in a universal format and are capable of working (although this has almost no practical value) in a regular PCI 2.2/2.3. In difficult cases, in order to be completely confident in the functionality of the combination of the motherboard and expansion card, you need to look at the compatibility lists of the manufacturers of both devices.

    PCI-X 2.0

    PCI-X 2.0 - further expansion of the capabilities of PCI-X 1.0; frequencies of 266 and 533 MHz have been added, as well as parity error correction during data transmission (ECC). Allows splitting into 4 independent 16-bit buses, which is used exclusively in embedded and industrial systems; The signal voltage has been reduced to 1.5 V, but the connectors are backward compatible with all cards using a signal voltage of 3.3 V. Currently, for the non-professional segment of the high-performance computer market (powerful workstations and servers entry level), in which it finds application PCI-X bus, very few motherboards with bus support are produced. An example of a motherboard for this segment is ASUS P5K WS. In the professional segment it is used in RAID controllers and SSD drives for PCI-E.

    Mini PCI

    Form factor PCI 2.2, intended for use mainly in laptops.

    PCI Express

    PCI Express, or PCIe, or PCI-E (also known as 3GIO for 3rd Generation I/O; not to be confused with PCI-X and PXI) - computer bus(although at the physical level it is not a bus, being a point-to-point connection), using software model PCI buses and a high-performance physical protocol based on serial data transmission. The development of the PCI Express standard was started by Intel after abandoning the InfiniBand bus. Officially, the first basic PCI Express specification appeared in July 2002. The development of the PCI Express standard is carried out by the PCI Special Interest Group.

    Unlike the PCI standard, which used a common bus for data transfer with multiple devices connected in parallel, PCI Express, in general, is a packet network with star topology. PCI Express devices communicate with each other through a medium formed by switches, with each device directly connected by a point-to-point connection to the switch. In addition, the PCI Express bus supports:

    • hot swap cards;
    • guaranteed bandwidth (QoS);
    • energy management;
    • monitoring the integrity of transmitted data.

    The PCI Express bus is intended to be used only as a local bus. Since the PCI Express software model is largely inherited from PCI, existing systems and controllers can be modified to use the PCI Express bus by replacing only the physical layer, without modifying the software. The high peak performance of the PCI Express bus allows it to be used instead of AGP buses, and even more so PCI and PCI-X. De facto, PCI Express replaced these buses in personal computers.

    • MiniCard (Mini PCIe) - replacement for the Mini PCI form factor. The Mini Card connector has the following buses: x1 PCIe, 2.0 and SMBus.
    • ExpressCard - similar to PCMCIA form factor. The ExpressCard connector supports x1 PCIe and USB 2.0 buses; ExpressCard cards support hot plugging.
    • AdvancedTCA, MicroTCA - form factor for modular telecommunications equipment.
    • Mobile PCI Express Module (MXM) is an industrial form factor created for laptops by NVIDIA. It is used to connect graphics accelerators.
    • PCI Express cable specifications allow the length of one connection to reach tens of meters, which makes it possible to create a computer whose peripheral devices are located at a considerable distance.
    • StackPC is a specification for building stackable computer systems. This specification describes the expansion connectors StackPC, FPE and their relative positions.

    Despite the fact that the standard allows x32 lines per port, such solutions are physically quite bulky and are not available.

    Year
    release    		 Version
    PCI Express    		 Coding Speed
    transfers    		 Bandwidth on x lines
    ×1 ×2 ×4 ×8 ×16
    2002 1.0 8b/10b 2.5 GT/s 2 4 8 16 32
    2007 2.0 8b/10b 5 GT/s 4 8 16 32 64
    2010 3.0 128b/130b 8 GT/s ~7,877 ~15,754 ~31,508 ~63,015 ~126,031
    2017 4.0 128b/130b 16 GT/s ~15,754 ~31,508 ~63,015 ~126,031 ~252,062
    2019
    		5.0 128b/130b 32 GT/s ~32 ~64 ~128 ~256 ~512

    PCI Express 2.0

    The PCI-SIG released the PCI Express 2.0 specification on January 15, 2007. Key innovations in PCI Express 2.0:

    • Increased throughput: bandwidth of one line 500 MB/s, or 5 GT/s ( Gigatransactions/s).
    • Improvements have been made to the transfer protocol between devices and the software model.
    • Dynamic speed control (to control the communication speed).
    • Bandwidth Alert (to notify software of changes in bus speed and width).
    • Access Control Services - Optional point-to-point transaction management capabilities.
    • Execution timeout control.
    • Function level reset is an optional mechanism for resetting PCI functions within a PCI device.
    • Redefining the power limit (to redefine the slot power limit when connecting devices that consume more power).

    PCI Express 2.0 is fully compatible with PCI Express 1.1 (old ones will work in motherboards with new connectors, but only at 2.5 GT/s, since older chipsets cannot support double the data transfer rate; new video adapters will work without problems in old PCI Express 1.x slots).

    PCI Express 2.1

    In terms of physical characteristics (speed, connector) it corresponds to 2.0; in the software part, functions have been added that are planned to be fully implemented in version 3.0. Since most motherboards are sold with version 2.0, having only a video card with 2.1 does not allow you to use 2.1 mode.

    PCI Express 3.0

    In November 2010, the specifications for PCI Express 3.0 were approved. The interface has a data transfer rate of 8 GT/s ( Gigatransactions/s). But despite this, its actual throughput was still doubled compared to the PCI Express 2.0 standard. This was achieved thanks to a more aggressive 128b/130b encoding scheme, where 128 bits of data sent over the bus are encoded in 130 bits. At the same time, full compatibility with previous versions PCI Express. PCI Express 1.x and 2.x cards will work in slot 3.0 and, conversely, a PCI Express 3.0 card will work in slots 1.x and 2.x.

    PCI Express 4.0

    The PCI Special Interest Group (PCI SIG) stated that PCI Express 4.0 could be standardized before the end of 2016, but in mid-2016, when a number of chips were already being prepared for production, media reported that standardization was expected in early 2017. will have a throughput of 16 GT/s, that is, it will be twice as fast as PCIe 3.0.

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    Hello, friends.

    For many years now, motherboards have been equipped with slots of the PCI-E standard, which has supplanted its progenitor PCI and its even more outdated predecessor AGP. However, this standard has several subtypes, and they can be located on the motherboard at the same time.

    This often misleads users when choosing hardware for their computer. In my article I will talk about PCI Express x16, since this specification is the most in demand these days, and you will be able to distinguish it from others.

    Briefly about PCI-E

    For those who are not in the know, first of all, I’ll explain in a nutshell what PCI Express actually is. This is the name of a modern computer bus, which is designed to transfer data between functional blocks of a PC.

    However, in physical terms, this is not a bus, but a point-to-point connection, that is, it directly connects two devices. What can be connected? Can connect the motherboard with video, audio and network cards, Bluetooth and Wi-Fi modules, specialized diagnostic controllers and other devices. But mainly in this video card slot.

    First of all, PCI-E generations should be distinguished. Nowadays, the most common is 3.0, but it is already being actively replaced by its successor, as it works twice as fast. Specification 5.0. will appear only in 2019.

    All generations of the standard have the same appearance tracks on the motherboard. But their length may be different. In particular, 4 main sizes: PCI Express x16, x8, x4, x1. The higher the number, the wider the contact area.

    The number of maximum connections that the interface is capable of transmitting to the card and back depends on the form factor. It is more correct to call these connections lines, which consist of two signal pairs: one transmits information, the other receives. The data transfer speed is determined by the PCI-E version.

    Speeds and compatibility

    To help you better understand what I'm talking about, check out the table:

    Version Connections (gigabytes per second)
    x1 x2 x4 x8 x16
    1.0 0.25 0.5 1.0 2.0 4.0
    2.0 0.5 1.0 2.0 4.0 8.0
    3.0 0.98 1.97 3.94 7.88 15.8
    4.0 1.96 3.94 7.88 15.75 31.5
    5.0 3.93 7.88 15.75 31.51 63.0

    The throughput of PCI Express x16 in the most common third generation today is 4 GB/s in each direction. Multiplying them together, we get a total figure of 16 GB/s, but in practice it is slightly less. This is quite enough for modern video cards.

    Keep in mind that a smaller form factor device can be inserted into a larger slot, but it will run at its own speed. For example, a video card has an x4 interface, and a motherboard has an x16 interface; They are compatible with each other, but the slot is not capable of adding power to the device. In turn, inserting a device with a larger interface than the motherboard has is not even physically possible.

    That's all.

    Brief history...

    For the first time, a separate interface designed to becomea replacement for the PCI bus for video cards, was introduced in 1997. AGP (from the English Accelerated Graphics Port, accelerated graphics port) - this is how Intel presented its new development simultaneously with the official announcement of the chipset for Intel processors Pentium II.

    Claimed benefitsAGP before its predecessorPCIwere significant:

    • higher operating frequency (66 MHz);
    • increased bandwidth between the video card and the system bus;
    • direct transfer of information between the video card and RAM, bypassing the processor;
    • improved power system;
    • high-speed access to shared memory.

    Due development standardAGP 1x (AGP 1.0 specification) was not received due to the low speed of working with memory and was almost immediately improved, and its speed was doubled - this is how the AGP 2x interface appeared. Transmitting 32 bits (4 bytes) per clock cycle, the AGP 2x port could deliver a peak performance unprecedented at that time of 66.6x4x2=533 MB/ s.

    In 1998, the AGP 4x standard (AGP 2.0 specification) was released, providing transmission of up to 4 blocks of information per clock cycle. At the same time, the signal voltage of the port was reduced from 3.3 to 1.5 V. The maximum throughput of AGP 4x became about 1G.B./ s. Subsequently, the development of specifications was protracted - the reason for this was the very low speed of the video accelerator fleet that existed at that time, as well as the low exchange rate with RAM.

    As soon as technical progress hit the bus, which turned out to be too small to transmit huge flows of information with modern video cards, a new standard was approved - AGP 8x (AGP 3.0 specification). As you may have guessed, it can transmit up to 8 blocks of information per clock cycle and has a peak throughput of 2G.B./ s. The AGP 8x bus is backward compatible with AGP 4x.

    The technology industry is always on the rise. The volumes of transmitted and transmitted data are increasing, textures and their quality are growing, all this certainly forces each of the manufacturers to give themselves a shake-up and come up with something new and high-tech (standard, specifications, protocol, interface) that will connect with themselves a new revolution in the fieldhi- tech.

    Officially, the first basic PCI Express specification appeared in July 2002, thereby marking the day of the gradual “departure” of AGP 8x...

    Introduction

    At the moment, the modern Intel P45/X48 chipset has official support for PCI Express 2.0 specifications, which the very common Intel P35 could not boast of. For those who are just planning to purchase a modern motherboard on the Intel platform, the choice remains quite obvious - the P45/X48 chipset, and you will not have the dilemma of “is PCI Express 1.1 enough or not enough for the current hi-end or middle-end video card. But what about the owners of P35s? Is it worth running to the store again?

    In our material today we will try to dot all the “Is” regarding the advantages of PCI-E 2.0 over PCI-E 1.1 for modern accelerators. We will also experimentally analyze the performance of video cards when working with various interfaces, on the basis of which a conclusion will be drawn about the practical value of PCI-E 2.0.

    And before we begin any objective tests, let's delve a little deeper into the theory, namely, let's figure out how it all works.

    PCI- Express- briefly about the main thing

    As mentioned above, the core PCI Express specification appeared in July 2002. Thanks to high speed and peak performance, the PCI Express bus leaves no chance to its predecessor AGP. According to its program model new interface PCI-E is in many ways similar to PCI, which makes it easy to adapt the current fleet of all kinds of devices to the new interface without significant software adjustments.

    Principle PCI work Express is based on serial data transmission. The bus is a packet network with a star topology. When PCI-E devices communicate, a bidirectional point-to-point connection is used, called "Line". Each PCI Express connection can consist of one (1x) or multiple lanes (4x, 16x, etc.).

    For a basic PCI-Express 1x configuration, the theoretical throughput is 250 MB/s in each direction (transmit/receive). Accordingly, for PCI-E x16 this value is 250 MB/s x 16 = 4 GB/s.

    It is noteworthy that from the physical side the interface allows, for example, any board with a PCI-E 1x interface to confidently work not only in standard mode, but also in any other mode. PCI slot Express with higher bandwidth (4x, 16x, etc.). Wherein maximum amount the lines involved depends only on the properties of the device.

    In all high-speed protocols, the issue of noise immunity always arises. To this end, PCI Express uses the long-known 8/10 or excess traffic scheme (8 bits of data transmitted over the channel are replaced by 10 bits, thus generating additional information, about 20% of the total “flow”).

    PCIExpress 2.0

    The standard was officially approved on January 15, 2007. In the second revision of PCI Express, the throughput of one channel has significantly increased - up to 5 Gb/s (PCI Express 1.x - 2.5 Gb/s). This means that now for the x16 line maximum speed data transfer can reach 8 GB/s in both directions versus 4 GB/s for the old PCI Express 1.x.

    A remarkable fact is that PCI Express 2.0 is fully compatible with PCI Express 1.1. In practice, this means that old video cards will work smoothly in motherboards with new connectors, and new video adapters will work without problems in old PCI Express 1.x connectors.

    Perhaps, let’s wrap this up with the theory and main features of PCI Express, it’s time to start the relevant tests, which, in fact, is what we will do, although a little lower, but for now let’s get to know the testing participants in detail.

    About the test participants

    Unfortunately, it was not possible to cover a larger set of graphics accelerators at the time of testing, which we will definitely fix in the future. Low-End class video cards were deliberately excluded from the tests, since they are of little use for high-resolution modes (over 1280x1024) with maximum picture detail, where the advantages of PCI-E 2.0 over the lower PCI-E 1.1 can be revealed.

    Video card

    Point Of View GeForce GTX 280

    POV GeForce 9600 GT 512 MB Extreme Overclock

    Palit HD 4850 Sonic

    Chip code name

    Technical process